Certain analysis and design of low power multipliers with various full adders to enhance energy efficiency in environmental protection and ecology

Abstract

Designing low power multipliers is essential for creating and using newlinepower efficient devices. Researchers have acknowledged the significance of newlinecreating low power multipliers. Very few studies have produced low power newlinemultiplier circuit designs. The present study is focused on creating low power newlinemultipliers utilizing three specific circuit designs. This research aims to newlineinvestigate various adder circuits used in creating multipliers and examine the newlinerelationship between power and area complexity of the adders. It also involves newlineevaluating existing multiplier designs, identifying their advantages and newlinedisadvantages, and proposing 4x4 multipliers - Wallace Tree multiplier and newlineDadda multiplier designs based on three different full adders: 8T adder, Hybrid newlinefull swing full adder, 6T adder. Additionally, the study will conduct a newlinecomparative analysis of the proposed multiplier designs based on transistor newlinecount and power consumption. newlineMultiplication is a crucial function in Digital Signal Processing (DSP) newlineunits, essential for high-speed communication networks and multimedia newlineapplications. Designing high-speed integrated circuits with minimal power newlineconsumption is a major concern for VLSI circuit designers. Full adders are newlineprimarily used for most arithmetic operations in digital circuits and are the main newlinecomponent that consumes a significant amount of power. Identifying the newlineoptimal multiplier architecture is a key consideration in the design of a Digital newlineSignal Processor. Multipliers are the primary contributors to power newlineconsumption in DSP. By lowering the multiplier s power consumption, the newlinedigital signal processor s power consumption may be decreased throughout a newlinelarge range. newline