Implementation of efficient carry select adder and floating point multiplier in vlsi design

Abstract

Carry Select Adder (CSLA) calculates the sum of double bit numbers of n+1 bit. In order to minimize the criteria of the previous framework, the design of the CSLA enhances the parameters of adder to give better performance. In phase 1, the Modified 16-bit SQRT with Modified Area Efficient CSLA is proposed to minimize power, area and delay. The minimized number of gates provides better performance over the existing models in terms of area, power and delay. The compared outcome demonstrates the proposed Modified SQRT CSLA that has improved and gives low utilization of area and power. The product of power-delay and area-delay of the proposed structure has been enhanced and shows the technique improvement yet not a delay of mere trade-off for power and area. Moreover, the proposed circuit demonstrates the effectiveness and the performance with less area, less power, efficient and simple for VLSI hardware implementation. In phase 2, the MAE-CSLA adder is proposed by removing the multiplexer which selects the yield dependent on the carry input. The removal of MUX and the resulting performance varieties are defeated by the AOI structure. At that point the MAE-CSLA is structured and its performance is calculated.It is seen as superior to the previous CSLA design. The principal point of the proposed design is to minimize the area utilization and it is achieved effectively. The comparison of outcomeanalysis demonstrates that the proposed CSLA has improved low power and area utilization. newline