Performance analysis and benchmarking of tunnel transistors with circuit co design for energy efficient and reliable computing architectures

dc.contributor.guide	Rama Krishna K
dc.coverage.spatial	Electronic and communication engineering
dc.creator.researcher	Shaik, Sadulla
dc.date.accessioned	2020-03-30T06:44:10Z
dc.date.available	2020-03-30T06:44:10Z
dc.date.awarded	n.d.
dc.date.completed	2017
dc.date.registered	n.d.
dc.description.abstract	file attached
dc.description.note	bibliography p. 128-152
dc.format.accompanyingmaterial	None
dc.format.dimensions	-
dc.format.extent	153 p.
dc.identifier.uri	http://hdl.handle.net/10603/286309
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Guntur
dc.publisher.university	Acharya Nagarjuna University
dc.relation	-
dc.rights	university
dc.source.inflibnet	INFLIBNET
dc.subject.keyword	Complementary Metal Oxide Semiconductor
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	Integrated Circuit
dc.subject.keyword	Reliable Computing Architectures
dc.subject.keyword	Tunnel Field Effect Transistors
dc.subject.keyword	Tunnel Transistors
dc.title	Performance analysis and benchmarking of tunnel transistors with circuit co design for energy efficient and reliable computing architectures
dc.title.alternative	-
dc.type.degree	Ph.D.