Gate all around stacked Nano wire Nanosheet Transistors for sub 7nm Technology Nodes

Abstract

The ever-increasing demand for faster, smaller, and more advanced devices necessitates newlineconstant innovation from the micro- and nanoelectronics industries. Today s emphasis on newlinelow-power and low-voltage operation in industry and academia requires an understanding newlineof the nanodevices at ultimate scaling. This research work focuses on advanced NW and newlineNS GAAFET devices design with technical depth and conceptual clarity. Predictive newlinecomputer-aided design and simulation approaches adopted provide several cutting-edge newlinenanodevices design solutions for 7nm technology nodes and below. newlineIn this research, we first present an overview of current and upcoming device structures newlinethat enable the continuation of device scaling. A brief overview of the state-of-the-art and newlinenext-generation semiconductor logic devices will pave the way for understanding the newlinechallenges involved in designing these devices. The NSFETs have been designed using newlinepredictive 3D TCAD simulations with important design parameters at the 7nm technology newlinenode. We have studied the effects of stacking multiple nanosheets for possible newlineperformance improvement of lateral nanosheet transistors using predictive simulation. We newlinehave explored the impacts of nanosheet width and thickness on electrical performance and newlineoutlined the important design guidelines necessary for vertically stacked nanosheet FETs. newlineThe performance of NSFET has been analyzed by comparing it with NWFET as well. newlineVertically stacked horizontal nanosheet gate-all-around transistors are shown to be one of newlinethe viable solutions toward scaling down below sub-7nm technology nodes. newlineWe have investigated the impacts of RDF and WFV in NSFETs. The 3-stack NSFETs newlineexhibit lower and#963;VTH and and#963;SS variation in the performance metrics compared to a single newlineNSFET. Furthermore, the impact of combined variability strongly influences both the VTH newlineand SS variation. We have observed that single, as well as stacked NSFETs, are more newlineimmune to WFV variations compared to NWFET. We have shown that vertically stacked newlineNSFET with the best immuni