Low power circuit design for footed quasi resistance scheme in 45nm VLSI technology

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dc.contributor.guideMUKESH TIWARI, VUNDELA PADMANABHAREDDY
dc.coverage.spatial
dc.creator.researcherTELUGU SATYANARAYANA
dc.date.accessioned2023-05-23T11:33:38Z
dc.date.available2023-05-23T11:33:38Z
dc.date.awarded2021
dc.date.completed2021
dc.date.registered2016
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/484938
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeSehore
dc.publisher.universitySri Satya Sai University of Technology and Medical Sciences
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleLow power circuit design for footed quasi resistance scheme in 45nm VLSI technology
dc.title.alternative
dc.type.degreePh.D.

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