Investigation on test pattern Generation and test power reduction Techniques for multiple stuck at faults

Abstract

newlineVery Large Scale Integration VLSI technology is a major newlinemilestone in the development of solid state electronics The advancement in newlineVLSI technology has allowed the integration of more and more functionalities newlineinto a single chip The chip density physical design fabrication and testing newlinecomplexity have therefore increased exponentially Hence testing of VLSI newlinecircuits plays a key role in the design flow and has become a challenging task newlinefor design and test engineers When the chip density was less majority of the newlinefaults were single stuck at faults and hence this model was sufficient to model newlineall the faults However with increased chip density this may not be the case newlineRecent empirical data from a real life design environment for 453 failing newlinedevices show that 41 of the defects found cannot be modeled with a single newlinefault Additionally 22 of the remaining 59 defect cases cannot be newlinemodeled using the single stuck at fault model Therefore in more than 60 of newlinethe cases where a chip is returned for defect analysis multiple stuck at fault newlinediagnosis is required and the classical single stuck at fault model may be newlineinadequate Liu and Veneris 2005 In a circuit with n lines there are around newline3n 1 multiple stuck at faults when compared to 2n single stuck at faults This newlineagain posed a problem because a large number of faults involve a large search newlinespace This problem of large search space combined with the problem of newlinestoring huge data from the fault simulator made test pattern generation for newlinemultiple stuck at faults a challenging task newline