Modeling and Simulation of Subthreshold Characteristics of Back Gated Soi Junctionless Field Effect Transistor JLFET

Abstract

The present era is of cloud computing, internet of things (IoT) and social media with smart newlinehandheld devices which are always in ON state. Such electronic devices need high data newlinetransmission rate and are driven by long battery life. In modern day, low power electronics newlinelargely depends on the MOS transistors which are fundamental building blocks of CMOS newlineintegrated circuits. The performance of MOSFET critically affects the performance of an IC. newlineWith the unabated scaling of the MOSFETs, the fabrication process technologies and basic newlinestructure of MOSFET are altering rapidly to make pace with the current need of IC newlinemanufacturing. The requirement of device structure which may render high performance with newlinelow power dissipation makes the Junctionless (JL) transistors an excellent choice. The JL newlinetransistors are believed to be potential candidates to carry on device scaling below 10 nm. newlineFurther, the blend of JLFET with SOI technology offer better immunity to low dimensional newlineeffects, low leakage with effective capacitance and better reliability. The study of subthreshold newlinecharacteristics in terms of threshold voltage, subthreshold current, subthreshold swing and drain newlineinduced barrier lowering are an important aspect of any CMOS device to determine the effects of newlineshortening of gate-length on the switching characteristics of the device.