Design of robust sub-threshold circuits for ultra low power moderate throughput applications

Abstract

There are two sources of power consumption in CMOS namely dynamic and leakage. The dynamic power in CMOS is a quadratic function of the supply voltage and the leakage power is its exponential function. Hence, the most effective way to reduce the power consumption is through supply voltage scaling. The extreme case of supply voltage scaling is the subthreshold regime in which it is scaled below the threshold voltage to achieve ULP. The leakage current is used as a driving current in subthreshold circuits and therefore, the speed degrades considerably. The design of ULP digital circuits has received widespread attention due to the rapid growth of ULP applications like body sensor networks and implantable medical electronics etc. Despite the speed degradation, few researchers have tried to improve the speed under subthreshold conditions. This thesis presents innovative techniques to enhance the speed and robustness of subthreshold circuits with a limited power budget to widen their application domain. There is a significant market for ULP applications which is currently being dominated by ASIC. The cost of ASIC is exponentially rising due to high NRE cost. Hence, it is important to extend the domain of FPGA even under subthreshold conditions so that they can also be employed for reconfigurable ULP applications in place of the expensive and more rigid ASICs in future technologies. This thesis proposes a low power FPGA routing switch box that utilizes the leakage current for body biasing. This technique significantly enhances speed, lowers switching energy, and increases robustness. The device optimized for superthreshold circuits may not provide the optimum subthreshold performance. Hence, FPGA interconnect resources performance has been enhanced using newlinedevice optimisation techniques under subthreshold conditions. The interconnect primarily determines the performance of systems at the nanoscale. Hence, the design of interconnect is crucial in improving the performance under subthreshold conditions.