Design and implementation of approximate computing circuits for error tolerant image processing applications

Abstract

Low power has become an important concern in the design of Very Large Scale Integration (VLSI) circuits. In recent years, approximate computing techniques improve the performance in terms of execution time, area, and power or energy with trade-off in accuracy. Applications that are both computation intensive and error tolerant are more suitable to adopt approximation strategies. The idea behind approximate computing is to introduce approximations at various design levels ranging from software, algorithm, architecture, logic or transistor levels. This thesis presents the wayto introduce the approximate computation at logic level of VLSI computing circuits such as adder, multiplier, subtractor, and divider. In this thesis, framework for evaluating approximate adders, approximate subtractors, approximate multipliers and approximate dividers have been proposed by improving the performance with trade-off in accuracy. The hardware implementation of these approximate computational circuits for Sobel edge detection has been presented. An adder is the basic computational circuit in digital VLSI design. To improve the design metrics of adder, Approximate Adders (AAs) have been proposed. These adders have been applied and analyzed on 8×8 Wallace Tree Multipliers (WTM) and Dadda multipliers. The design metrics of proposed AAs, Approximate Wallace Tree Multipliers (AWTM) and approximate Dadda multipliers are synthesized in Cadence Register-Transfer Level (RTL) compiler and compares the design metrics with three different technology nodes. newline