Design and management of distributed shared memory with multicore architectures

Abstract

quotDesign and Management of Distributed Shared Memory with Multicore Architectures newline newlineSubmitted By: Vasava Hemantkumar Dineshbhai, Assistant Professor, BVM Engineering College, Vallabh Vidhyanagar, Ph.D. scholar, Faculty of Technology, RK University Rajkot. Gujarat, India. newline newlineSupervised By: Dr. J.M. Rathod, PhD (Electronics Engineering), Associate Professor, Electronics Department, BVM Engineering College, V.V.Nagar, Gujarat, India. newline newlineAddress of Workplace: BVM Engineering College, Computer Engineering Department, V.V.Nagar, Gujarat, India. newline newlineKeywords IPC, DSM, Granularity, DGAS, Page fault, Thrashing, Virtual Address Space, Lookup newlineBackground: Distributed and parallel processing systems are one of the most advanced area of research today. They provide the shared memory construct in systems with physically distributed memories and consequently combine the advantages of both approaches. A distributed shared memory (DSM) is the popular exploration areas in multiprocessor network. It has been measured by researchers from diverse areas of sciences and engineering. It is require to optimize distributed shared memory performance for building high performance, large scale multiprocessor systems. Much research has been carried out in the past which overcome number of limits but the achievable issue still persists DSM algorithm, locking shared space, thrashing, concurrent access, page fault, extension, transparency, large database support and cost. These thesis focused on new distributed shared memory design using software parameters that give significant performance improvement compared to conventional structural design to manage software distributed shared address space. This research also discusses various factors that exist while moving toward software distributed shared memory implementation. newline newline newlineAim: The main aim of this research is to develop new distributed shared memory architecture using software approach. The goal is to develop and implement efficient algorithm and low latency rate. newline newlineMaterial and Methods: This research