Digitally intensive Sub Sampling Mixer First RF front End architectures in 1 2 V 65nm CMOS

Abstract

Abstract newlineTo meet the ever-growing need for connected devices, advanced wireless systems have newlineto accommodate tens of billions of wireless devices to support a wide range of applications newlinein various communication standards. The wireless communication standards such as newlineIEEE 802.15.4-2020 are designed to provide better coverage for low-cost, portable wireless newlinesystems with limited power consumption for various applications such as smart utility newlinenetworks(SUN), rail communications and control(RCC), healthcare and industrial monitoring. newlineThese applications operate in multiple bands over a wide frequency range from newline0.16 GHz to 2.4 GHz and have low data rates; hence, they should consume low power newlinefor long battery life. To meet these requirements, the receiver s RF front-end must be newlinere-configurable, and power consumption needs to be low while maintaining the sensitivity newlineof the receiver. The mixer-first RF front-end architecture operates over a wide range of newlinefrequencies by tuning its local oscillator frequency or sampling frequency(fs). Therefore, newlinea single mixer-first RF front-end is sufficient to cover complete or most of the sub-2.4 GHz newlineIEEE 802.15.4e standard applications. newlineThe mixer-first receivers employ N-path mixers and filters, which are excited by nonoverlapping newlineclock phases and hence require clock dividers to generate precise multi-phase newlinenon-overlapping clocks. These dividers require a reference clock frequency of Nfs/2 for newlinegenerating non-overlapping clocks with a frequency, fs. In RF sampling-based mixer-first newlineRF front-ends requires a sampling frequency greater than or equal to fs, which increases newlinethe power consumption of these non-overlapping clock generation and distribution circuitry newlineincreases with the increasing fs. In addition, the stringent jitter requirements increase the newlinepower consumption of the frequency synthesizers at high frequencies. Hence, the power newlineconsumption of the clock generation circuit is no longer negligible since it increases with the newlineinput RF frequency, fRF . On the other hand, the sub-samplin