VLSI Implementation of 2D DCT Image Compression using Pipelined Architecture

Abstract

The simulation has been done in Vertex-4. The RTL view is in figure number 8.8.1, newlineRTL schematics view figure number 8.8.2(a), (b),(c), technology schematics view is in newlinefigure number 8.8.3 (a), (b), (c), (d), (e),(f) and design summary is in figure number newline8.8.4, table based on design summary in on table number 8.7 and graphical view for newlinethis summary on figure number 8.8.6. After examine these figures, tables, and format newlineprécis it is concluded that the no. of slices is 7246, no. of flip-flop is 3878, no. of 4 newlineinputs LUT s is 11210 and no. of IOB s is 168. It is also observed that the area newlineutilization is decreased so processor performance has been increased. newline newline