Design and implementation of efficient approximate multipliers for digital image processing

Abstract

Arithmetic and Logic Unit (ALU) is the essential component of digital newlinesignal and image processing systems. Adders and multipliers are the essential newlinecomponents in design of digital processing hardware. However, the multiplier newlineis the significant element that contributes for the total delay and hardware newlinecomplexity in Complementary Metal Oxide Semiconductor (CMOS) newlinehardware design. Hence in this research, an effort is made to design novel newlinearchitectures for multiplier using approximate computing targeting error newlineresilient applications in digital image and signal processing. The proposed newlineapproach concentrates on multiplication algorithm modeling, architecture newlinedesign using Hardware Description Language (HDL) model, functional and newlineperformance analysis, and driving capability and novelty verification through newlinereal time implementations. newlineA low power area efficient approximate multiplier that uses two new newlinevariants of 4:2 approximate compressors for Partial Product (PP) newlineaccumulation is proposed. The proposed compressor 1 designated as PC-1 newlinegenerates minimal error compared to prior approaches and the proposed newlinecompressor-2 designated as PC-2 demonstrates fewer gate count when newlinecompared to PC-1 and other prior designs. The multiplier performs PP newlinecompression in stages using Carry save addition with dadda structure based newlinePP arrangement. In the final stage, the PPs are reduced into two rows of sum newlineand carry signals and are added using Ripple Carry Adder (RCA). newline