Process Variation Tolerant High Speed Domino Logic Keeper Circuit Designs

Abstract

The feasibility of operating domino logic circuits at high speed in deep sub newlinemicron regime is limited by its noise tolerance capability. The inclusion of keeper newlinecircuit to counteract this limitation of domino logic circuits leads to degradation of newlinespeed performance. Hence, the design and incorporation of appropriately controlled newlinekeeper circuits in domino logic circuits are necessitated. newlineThree styles of clock controlled keeper circuits for domino logic circuits have been newlineproposed in this research, which can offer high speed of operation with good robustness to noise characteristics. The Clock Controlled Dual keeper Domino with AND keeper control (CCDD 1) and Clock Controlled Dual keeper Domino with T-gate control (CCDD 2) offer abrupt controlling of keeper circuit with dual transistor keeper newlinecircuit configuration and delayed enabling of the footer transistor using clock signal newline