Certain investigation on logic styles used in full adder for vlsi applications

Abstract

In the modern digital very large scale integration (VLSI) design, newlinethe explosive growth in usage of portable consumer products like laptop and newlinemobile phone devices, has motivated the researchers to achieve enhanced newlineVLSI systems. Full adder is the most important fundamental building block newlineof complex arithmetic circuits in digital systems like microcontrollers and newlinedigital signal processors. The performance of a single bit full adder can be newlineimproved by employing optimized logics for arithmetic operations. The newlineadder cell is a basic building block in VLSI systems and it determines the newlineoverall performance. Due to this reason, enhancing the performance of single newlinebit full adder cell in terms of power, speed and power delay product (PDP) is newlinea vital field of research. newlineIn the VLSI systems, the most important performance newlineparameters are power consumption, speed and reliability in function. The newlinedesign of a low power system is one of the major requirement to develop an newlineenergy efficient digital systems. The energy efficient system is attained by newlineincorporating effective power optimization techniques. Among several low newlinepower techniques, one of the important method is choosing proper logic newlinestyles at transistor level. The design of enhanced full adders with low power newlineis preferred to perform the arithmetic operations for VLSI applications. newline