Design and Reliability Analysis of Multistage Interconnection Network for Multiprocessor Systems

dc.contributor.guide	Yadav,Dilip Kumar and Choubey,Arvind.
dc.coverage.spatial
dc.creator.researcher	Amit Prakash
dc.date.accessioned	2023-01-09T12:24:38Z
dc.date.available	2023-01-09T12:24:38Z
dc.date.awarded	2020
dc.date.completed	2020
dc.date.registered	2017
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions
dc.format.extent
dc.identifier.uri	http://hdl.handle.net/10603/440124
dc.language	English
dc.publisher.institution	Department of Electronics and Communication Engineering
dc.publisher.place	Jamshedpur
dc.publisher.university	National Institute of Technology Jamshedpur
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	Design and Reliability Analysis of Multistage Interconnection Network for Multiprocessor Systems
dc.title.alternative
dc.type.degree	Ph.D.