Novel architectures for enhancing the performance of dsp functionalblocks in vlsi

Abstract

In the recent technological development of IC manufacturing withscaling down process, VLSI based system design has been drasticallyimpacted. With the advanced high speed system design more and morecircuits are integrated for fabrication to achieve higher and betterperformance. The three parameters namely area, delay and power of thedesign are very important. They are in trade off with each other. Among thethree parameters (area, delay and power) delay plays a vital role in manyarchitectures of VLSI based high level synthesis system design. The longestpath delay is called critical path delay. The critical path delay is the delaywhich determines the speed of the system. In system design, the total delay ofthe design is the algebraic sum of logic delay and path delay. Hence the speedis determined by logic delay and path delay. Reducing logic delay is difficultto achieve. So, the other choice is to reduce path delay to achieve betterperformance in high speed system design. A small modification at the leafcell or at sub-module level may lead to a path delay reduction in a system.Intra delay is the delay within the sub-module, whereas inter delay is thedelay between the sub-modules. This thesis proposes novel techniques forenhancing the performance of various DSP functional blocks in VLSI. Itbriefs the design and implementation of the architectures of DistributedArithmetic, BCD adder, systolic array multiplier, binary array multiplier,carry save multiplier, matrix multiplication, FFT and ROBDD. The modulesdesigned in this work find applications in VLSI based SoC, NoC and inembedded system design.