Investigation and Simulation to Design and Analysis of Novel Double Gate MOSFET

Abstract

Immense growth of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been seen in the scaling of the dimensions of MOSFET in the last few decades. With scaling the dimensions of the device, the speed increases along with packaging density and enhances the device s functionality. It has further decreased the chip cost and reduced power dissipation. However, the continuation of the scaling of the device below 22 nm, the technology node invites the challenges, called short channel effects (SCE s), which deteriorate the device s performance. The enhancement of gate control could restrict the short channel effects with the scaling of the device. The double-gate architecture enhances the gate controllability on the carriers such that leakage current and other short channel effects could be controlled even at smaller channel lengths. Another solution to improve the device s performance is by reducing the short channel effects with architectural changes. Various architectural changes have been done to enhance the functionality and performance of the MOSFET device even at smaller dimensions. This work introduces an innovative configuration for a double gate Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) and presents its simulation results. The configuration achieves the functionality of a Complementary Metal-OxideSemiconductor (CMOS) inverter through the integration of p-type and n-type MOS transistors within a single device. In contrast to the conventional CMOS inverter, our proposed device employs a single substrate, streamlining its structure. Additionally, the proposed design exhibits a notable reduction in short-channel effects at smaller channel lengths. Remarkably, when the channel length (Lg) is set to 50 nanometers, the proposed inverter demonstrates exceptional Voltage Transfer Characteristics (VTC) curve, Static Noise Margin (SNM), and V-curve. These performance parameters exhibit favorable values for both p-mode and n-mode operations. newline