An investigation on performance analysis of VLSI non slicing floorplanning using heuristic optimization methods

dc.contributor.guide	A, Senthilkumar
dc.coverage.spatial	Information and Communication Engineering
dc.creator.researcher	P, Sivaranjani
dc.date.accessioned	2018-03-15T11:46:10Z
dc.date.available	2018-03-15T11:46:10Z
dc.date.awarded	n.d.
dc.date.completed	2016
dc.date.registered	n.d.
dc.description.abstract	Abstract available
dc.description.note	Data not available
dc.format.accompanyingmaterial	None
dc.format.dimensions	8cm.
dc.format.extent	xx, 131p.
dc.identifier.uri	http://hdl.handle.net/10603/196090
dc.language	Others
dc.publisher.institution	Faculty of Information and Communication Engineering
dc.publisher.place	Chennai
dc.publisher.university	Anna University
dc.relation	119-129
dc.rights	university
dc.source.university	University
dc.subject.keyword	Algorithm
dc.subject.keyword	Flocrplanning
dc.subject.keyword	Floorplan
dc.subject.keyword	Partitioning
dc.subject.keyword	Wirelength
dc.title	An investigation on performance analysis of VLSI non slicing floorplanning using heuristic optimization methods
dc.title.alternative
dc.type.degree	Ph.D.