Integrating Power and Clock Distribution Networks in a SoC

Abstract

The challenge of reducing the power consumption in a system-on-chip (SoC) is a never ending job for engineers. The complexity of circuits is increasing in recent years to meet the functional demands of the industry. The circuit designers have tried various techniques and one such attempt is to merge the power and clock networks. There are references of decade long efforts in this regard. In this work we have explored various circuits capable of optimizing power utilization in a system-on-chip. One of the circuits is a CMOS based oscillator circuit made up of capacitors and magnetic inductors. This circuit generates a signal which is a combined power and clock signal used for driving the combinatorial part of the circuit. The sequential part of the circuit is driven by demerging the signal to get a normal full swing clock signal. This can be attained by a clock buffer unit which is designed on the principle of a Schmitt Trigger circuit. The results obtained after simulating the circuit shows an optimized consumption of 2.5µW of power. newline