VLSI implementation of digital cryptosystem for internet of things

Abstract

The main goal of this work is a design of the low area high speed and completely protected architecture for the Internet of Things IoT applications We gave more importance to the developments of hardware constructions and protected information communication for the Internet of Things IoT applications using pipelined Advance Encryption Standard AES and 10 stage pipelining AES Substitution box S box algorithm Advanced Encryption Standard AES is the best technique for consistent data transfer in the field of medical communication IoT ATM satellite communication E Commerce and Net Banking etc Advanced Encryption Standard performs the main role in protected data communication The main requirement of data communication is transfer data without error from input to output AES S box the Sub Bytes transformation is the costliest and performance critical module block in AES hardware circuitry It also takes up the most power consumption in the AES circuit owing to the excessive occurrence of dynamic hazards Thus the non linear S box is the major bottleneck in achieving small area high speed and low power AES hardware implementations AES S box hardware implementation can be categorized into three major paradigms newline