Modeling and Performance Improvement Techniques for GNR and CNT On Chip Interconnect

Abstract

The emerging VLSI technology and simultaneously highly dense packaging of devices and interconnects in Nano-scale chips have prosperously enabled realization of system-on-chip (SoC) designs and advanced high-performance computing applications. Concurrently, these have aggravated inevitable challenges in miniaturized integrated circuits (ICs). One of the main limiters in the performance of high-speed VLSI circuits is the on-chip interconnects. newlineFuture interconnect materials like allotropes of carbon are suggested to be probable replacement of copper (Cu) interconnect as Cu interconnects are prone to problems encountered due to technology scaling down. Also, allotropes of carbon offer superior properties like high thermal conductivity and current carrying capacity compare to Cu interconnects. It is analyzed from the current research work that graphene interconnects possess better performance in terms of signal integrity issues like delay, power dissipation, crosstalk etc. compared to Cu interconnects. Also, various performance improvement techniques like conventional CMOS buffer insertion and Schmitt trigger-based buffer insertion techniques have been proposed to mitigate the issue of signal integrity for long on-chip Cu and graphene interconnect lines. newlineAs the technology shrinks, variation due to temperature, fabrication process and environmental fluctuations grows up significantly. This results in variation in output performance. Variability analysis for graphene interconnects has been proposed with various methods like process corner, parametric analysis and Monte Carlo simulations. Timing uncertainty issues related to eye-diagram like jitter, eye crossing parameter and eye-opening factor have been examined for on-chip MLGNR (multilayer graphene nanoribbons) interconnects in the present research work. newlineAlso, delay fault analysis has been carried for variants of carbon nanotubes (CNT) interconnects. A 10-stage inverter chain and a D flip-flop are used to mimic the SPICE based delay-fault model. The model proposed of