Implementation and Verification of Adaptable Scheduling Algorithm for Real Time Applications Using Concurrent Architecture

Abstract

Concurrent architectures are the modern tools and devices developed specially for rapid newlineprototyping of the top-notch technology. In the traditional devices, in which once the newlineintegrated circuit is fabricated then the functionality cannot be changed, the uniqueness newlineof concurrent architectures or the devices is like they are reconfigurable which means newlinethe functionality of the integrated circuit can be altered up to the endurance cycle. In newlinethe proposed research work titled implementation and verification of adaptable newlinescheduling algorithm for real time applications using concurrent architecture, an newlineintelligent scheduling algorithm is proposed which takes care of scheduling the newlineincoming tasks based on conditions arising on the real time conditions. newlineIn the development process, the architecture of the proposed system is described using newlinefundamentals of the Very High-Speed Integrated Circuit Hardware Description newlineLanguage (VHDL). Subsequently and the implementation is carried out using Xilinx newlineVivado High Level Synthesis Tool (HLS). The said architecture is first functional newlinesimulated to validate the logical correctness of the described VHDL program. Once the newlinelogical correctness of the VHDL code is verified, the same program is synthesized. The newlineprocess of synthesis is carried out in order to convert the logical or Boolean statements newlineinto executable hardware architecture. The process of functional verification and newlinehardware verification is done using Xilinx Vivado High Level Synthesis (HLS) Tool. newlineSubsequently, the tiny steps in the implementation are executed by targeting the newlinedescribed architecture to the different FPGA variants. Finally, the outcome is analyzed newlinewith respect to the different ascendency parameters like Time, Frequency, Power and newlineResource Utilization for implementation of the design. Finally, the architecture is newlinetightly optimized by importing the design into Cadence tool where Application Specific newlineIntegrated Circuit (ASIC) design flow is executed. In this design flow different to