Performance analysis of junctionless devices on planar and non planar structures

Abstract

Relentless march past of the CMOS scaling had slowed down due to short newlinechannel effects faced in the lower dimensions. Over the years, the scaling side newlineeffects in CMOS have been diagnosed in multiple ways. Some of the solutions newlineare LDD (Lightly doped drain), Halo doping, SSRC (Super steep retrograde newlinewell), metal gate and SOI. The junctionless approach in devices is another newlinesolution to the complex fabrication process involved in the case of scaled down newlinedevices. The thesis analyses three existing junctionless device structures, bulk newlineplanar junctionless device, bulk trigate junctionless device and junctionless newlinenanowire and nanotube. The effect of substrate doping and spacer newlinecharacteristics on device performance is analyzed in the planar structures. The newlineperformance of the Trigate structure is improved through isolation oxide and newlinegate. The impact of eccentricity on the nanowire and nanotube structures are newlinealso investigated. The thesis also proposes two new junctionless device structures, newlinejunctionless segmented FET and junctionless ringFET. Since, the channel newlinelength scaling in ringFET structure changes the width, the scaling trend is newlinedifferent from the other structures. Since junctionless devices work in the flat newlineband region they need more doping to increase the ON current which also newlineincreases the OFF current. Segmented substrate tries to reduce the OFF current newlinewithout compromising with the ON current, in the sense junctionless devices newlineon segmented substrate offer more gate control i.e. better ION/IOFF ratio even newlinethough the segmented substrate reduces ION. newline newline