Design of low power non volatile magnetic flipflop using FD SOI technology

Abstract

For almost 40 years the development of electronic circuits is evolving according to more or less Moore s law speed and density double every 18 months But in advanced technology nodes this trend tends to get out of breath Indeed due to the small dimensions of the devices and the high speed operations the power consumption of logic circuits becomes larger and larger resulting in heat dissipation and reliability issues Several techniques have been implemented to decrease the power consumption of logic circuits clock and power gating dynamic voltage frequency scaling Power gating consists in cutting off the power supply of unused blocks of a circuit to reduce the standby power consumption With volatile memories this technique requires copying the data into non volatile or very low leakage memory resulting in delays and dynamic power consumption Using a Non volatile flip flop NVFF allows cutting off the power supply without any additional operation and with very low area overhead allowing an efficient instant on/off policy In this way it allows the circuit to be stopped and restarted at once on demand with full performance leading to the concept of normally off electronicsand#8214; This also improves the circuit reliability in particular against power failures Radiation immunity is a further advantage of this hybrid CMOS Magnetic technology In this research a compact and high performance non volatile latch integrated into a flip flop and a full Magnetic Process Design Kit MPDK allowing full custom and digital design of hybrid CMOS Magnetic circuits newline