Reliability Aware Analysis and Design of Network on Chip

dc.contributor.guide	Gaur, Manoj Singh and Bhargava, Lava
dc.coverage.spatial
dc.creator.researcher	SHARMA, ASHISH
dc.date.accessioned	2022-01-24T09:53:12Z
dc.date.available	2022-01-24T09:53:12Z
dc.date.awarded	2019
dc.date.completed	2019
dc.date.registered	2013
dc.description.abstract	Attached newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	x, 155
dc.identifier.uri	http://hdl.handle.net/10603/357667
dc.language	English
dc.publisher.institution	Department of Computer Science and Engineering
dc.publisher.place	Jaipur
dc.publisher.university	Malaviya National Institute of Technology Jaipur
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computer Science
dc.subject.keyword	Computer Science Hardware and Architecture
dc.subject.keyword	Engineering and Technology
dc.title	Reliability Aware Analysis and Design of Network on Chip
dc.title.alternative
dc.type.degree	Ph.D.