Design of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique

dc.contributor.guide	Dhavachelvan, P.
dc.coverage.spatial
dc.creator.researcher	Uma, R.
dc.date.accessioned	2018-09-28T07:37:54Z
dc.date.available	2018-09-28T07:37:54Z
dc.date.awarded
dc.date.completed	2015
dc.date.registered	14/11/2011
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	xviii, 246 p.
dc.identifier.uri	http://hdl.handle.net/10603/217714
dc.language	English
dc.publisher.institution	Department of Computer Science
dc.publisher.place	Pondicherry
dc.publisher.university	Pondicherry University
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	low power
dc.subject.keyword	high speed
dc.subject.keyword	gate diffusion
dc.subject.keyword	input technique
dc.subject.keyword	accumulate unit
dc.title	Design of low power and high speed multiply accumulate unit using enhanced gate diffusion input technique
dc.title.alternative
dc.type.degree	Ph.D.