Design and implementation of efficient arithmetic circuits for processing applications

Abstract

Reducing power dissipation of CMOS integrated circuits is a major challenge in the design of portable systems and high performance processors The limited battery life due to lack of technology advancement in battery imposes strict demands on the overall performance of portable system In addition the smaller feature sizes not only allow integration of a larger number of components on a chip but also reduce the signal propagation delays which in turn permit higher clock frequencies at the expense of leakage power dissipation However larger number of devices on a die results in an overall increase in power dissipation posing special challenges on heat dissipation of architectures used in processing applications Thus the research orients towards reducing area and power dissipation in datapath elements of processing architectures by circuit and algorithmic level modifications Three classes of arithmetic circuits viz adders multipliers and counters are considered and explored at circuit and algorithmic level Adders are the key elements of Arithmetic and Logic Units and Multiply and Accumulate units used in image and signal processing architectures as they lie in the critical path However high integration necessitates reduced area and power dissipation newline