An Efficient High Speed Hierarchical Topology for Network on Chip Design of Mega Cmp Core Architecture Fractal Cone Topology

Abstract

High performance embedded applications are developed using newlinesystem-on-chips (SoCs) which includes silicon intensive, integrated newlineapplication processors sequentially. These SoCs integrate multi-core newlineprocessor (i.e., ARM Cortex9 or A15) with variety of memory interface newlinecontrollers, communication interface controllers and special purpose newlineaccelerators. Traditionally bus matrix is used for integrating these newlineintellectual property cores (IPs). Bus based architectures are not scalable newlineand consume more area and power, which has fueled design of network on newlinechip (NoC). In this research work, a methodology for customized NoC newlinearchitecture is introduced considering various aspects of NoC as well as newlinethe SoC. Policies for optimizing bandwidth requirement, size of the IP newline(area or gate count), IP location for optimum path lengths are conversed newlinefor competence which forms the methodology for optimum NoC newlineconsecutively. newlineAs IPs in SoC increase in numbers, NoC for interconnecting every newlineIP may result in over networking. For closely coupled IPs direct port to newlineport connections are suitable than NoC as they communicate heavily. IPs newlinewhich deliberate one at a time is grouped together and common local bus newlinearchitecture is suitable for them. Proper grouping and layout will reduce newlinecomplexity. Here I am proposing a methodology for handcrafting NoC newlineamong intellectual property core groups (IPGs), inside and outside of the newline newlinegroups. Final outcome is, reduced number of routers required and newlineoptimized physical design of SoC. newlineToday, advanced fabrication technologies promise us mega newlineintegration of processor cores on single chip. It is an era of multiprocessor newlineengines and parallel computing on chip. However, just integration of newlinemultiple PEs is not sufficient for these calculating monsters. Internally, newlinethey must be fortified with proper network. The NoC with appropriate newlinetopology is the only way to weave communication fabric for efficient newlineintegration of PEs. The key challenge is reducing the number of hops newlinerequired for data packets to reach from one end to other end processor core. newlineRegular topology fall less for mega core integration. Problems like slower newlinenetwork, traffic congestion and non-tolerable latency crop up. For efficient newlinecommunication between PEs the hierarchical network topology clubbed newlinealong with parallel network provides a solution. The proposed topology newlinereduces the number of hops taken by packets from source to destination newlinenodes and latency too is reduced with hybrid topology. The proposed newlinenetwork solution combines hierarchical, spidergon and star topology. An newlineattention is also given to the interconnecting router architecture for newlinehierarchy planes. newline newline newline