Area and power efficient testable hardware design using high level synthesis

Abstract

Nowadays, testing approaches are indispensible to test the design implemented on Programmable Logic Devices (PLDs). Field programmable Gate Arrays (FPGAs), one of the most widely used programmable devices in PLDs family, are difficult to test, due to their programmable nature, overall size, complexity, limited number of Input / Outputs (I/Os), and availability of large and variety of embedded cores on-chip. To ease the complexity of testing, several Design-For-Testability (DFT) techniques have been presented. Recently, the research community has been focusing on testing hardware at higher abstraction levels. Testability during the High-Level Synthesis (HLS) is called High Level Test Synthesis (HLTS), which has the following benefits: (i) reduced test hardware overhead, (ii) improved fault coverage, and (iii) reduced design iterations. Compared to DFT techniques applied at gate level circuits, HLTS makes the testing task easier, since it is done at higher newlineabstraction. The proposed work is a new methodology to incorporate testability with the Technology driven High-Level Synthesis (THLS), which is a customized High-level synthesis approach based on the target technology. This new methodology is called Testable Technology specific High-Level Synthesis (TTHLS), and it generates testable hardware from the corresponding HDL input. This new approach proposes Testable Technology Specific Library (TTSL), which has target technology specific test structures like scan flip-flop, Linear Feedback Shift Register (LFSR), etc. The testability incorporation at this higher abstraction, using this integrated approach, proves to be better in terms of area, and power consumption than the conventional newlineapproaches. newline newline