Circuit level optimization techniques for embedded architectures

Abstract

Technology scaling has increased the transistor s susceptibility to process variations in nanometer VLSI circuits. The effects of such variations are having a huge impact on performance and hence the timing yield of the integrated circuits. The circuit optimization objectives namely power, area, and delay are highly correlated and conflicting in nature. The inception of variations in process parameters have made their relationship intricate and more difficult to optimize. The growing market of portable (e.g., cellular phones, gaming consoles, etc.), battery-powered electronic systems demands microelectronic circuits design with ultra-low power dissipation. As the integration, size, and complexity of the chips continue to increase, the difficulty in providing adequate cooling might either add significant cost or limit the functionality of the computing systems, which make use of those integrated circuits. As the technology node scales down to 65nanometer there is no significant change in newlinedynamic power dissipation. However the static or leakage power is same as or exceeds the dynamic power beyond 65nm technology node. Scaling of technology node increases power-density more than expected. CMOS technology beyond 65nanometer node represents a real challenge for any sort of voltage and frequency scaling starting from 120nanometer node, each new process has inherently higher dynamic and leakage current density with minimal improvement in speed. Between 90nanometer to 65nanometer the dynamic power dissipation is almost same whereas there is ~5% higher leakage/mm2. newline newline