A power optimized 10 bit 100ms s pipelined Analog to digital converter for high Speed interface circuits

Abstract

High speed and medium resolution Analog to Digital Converters newline ADC are widely used in commercial applications including data newlinecommunication and image signal processing In such applications the newlinereduction of power consumption associated with high speed sampling and newlinehigh linearity is one key design issue in enhancing the portability and battery newlineoperation Among many ADC architectures pipelined ADC is proved to be newlinethe most suitable for high speed medium resolution and low power newlineconsumption Advancement in fabrication technology reduces the feature size newlineof the transistor and scales down the supply voltage To achieve high linearity newlinehigh dynamic range and high sampling speed simultaneously under low newlinesupply voltages in deep submicron Complementary Metal Oxide newlineSemiconductor CMOS technology with low power consumption has been newlineconsidered as extremely challenging Thus the objective of this work is to newlinedesign and implement a low voltage low power medium resolution and newlinehigh speed pipelined ADC in deep submicron CMOS technology newlineThe resolution per stage plays an important role in determining overall newlinepower dissipation of a pipelined ADC The pros and cons of both large and newlinesmall number of bits per stage are examined Based on the observations the newlinemost suitable resolution per stage architecture is selected to realize the newlinepipelined ADC newline