Linovo longevity enhancement of non volatile caches by placement write restriction and victim caching in chip multi processors

Abstract

The ever increasing demand for higher processing speed with hiked data parallelism force the computer architects to increase the number of processing cores on a single chip called Chip Multi processors CMPs Towards meeting the performance goals these CMPs are equipped with larger on chip Last Level Caches LLCs to enhance the probability of the presence of data on chip during process execution The existing literature portrays that conventional LLCs built in charge based memory technologies...