Architectures for online processing in reconfigurable computing

dc.contributor.guideDevanathan, R
dc.coverage.spatial
dc.creator.researcherGEORGINA RACHEL GEORGE
dc.date.accessioned2022-01-10T12:36:53Z
dc.date.available2022-01-10T12:36:53Z
dc.date.awarded2018
dc.date.completed2018
dc.date.registered2012
dc.description.abstractReconfigurable computing based on FPGAs can be used to compute just right enabling choice of nonstandard operators and newline on standard data types and sizes as required by a particular algorithm. Due to their bit-level granularity as newlineopposed to the word level granularity of processors, FPGAs are suitable platforms for hardware implementations of DSP algorithms and high performance floating-point computations over very large data sets that newlinecharacterize supercomputing applications. Spatial parallelism ensures speed up newlineand hardware pipelining further increases utilization of functional units in every newlineclock cycle. Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing newlinepipelining at digit level. newlineThe proposed work aims at developing algorithms and architectures for newlinemultiple-operand online processing of fixed and floating-point data on FPGAs. newlineThe operators synthesized using the proposed techniques are implemented on newlinethe Virtex 6 (xc6vlx75t-3ff484) FPGA. Analysis of higher radix and parameterized designs that represent a trade-off between throughput, latency, speed of operation and complexity enables the choice of a suitable data format.Architectures for online multiplication of fixed and floating-point numbers are newlinepresented. The proposed multipliers are designed using a technique to serialize newlineparallel multiplication and do not use serial-to parallel conversion or a selection newlinexiii newlinetable as in existing online algorithms, resulting in operators with reduced newlinecomplexity and accurate outputs. Implementations of online squaring, sum of newlinesquares and dot product operators demonstrate the efficiency of specialized newlinenonstandard online operators over parallel and general purpose online operators newlinethrough improvement in clock frequency and reduction in resource utilization. newlineA mathematical framework for a novel adaptation of the parallel shift-and-add newlinemultiplication algorithm
dc.description.note online floating-point multipliers; FPGA; higher radix; latency; throughput; cycle time
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/355114
dc.languageEnglish
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.publisher.placeChennai
dc.publisher.universityHindustan University
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleArchitectures for online processing in reconfigurable computing
dc.title.alternative
dc.type.degreePh.D.

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