Certain investigations on area efficient hardware architecture with aes encrytor and decryptor

Abstract

Advanced Encryption Standard (AES) is a widely adopted newlinecryptographic algorithm and it is considered secure in electronic information. newlineSince AES algorithm is fast and secure, it has become the global standard of newlineencryption. AES was approved to become the US federal standard and this newlinealgorithm is used to keep a significant amount of communications safe. newlineIn this research work, minimum area and less hardware utilisation newlineis achieved by the design of AES-128 encryption iterative architecture. A newlinerenovated S-Box structure is introduced into the AES algorithm to attain newlinereduced area. In addition, the Vedic multiplier is incorporated in the Mix newlineColumn transformation of the AES Encryption so that hardware utilisation is newlineminimized. The proposed encryption architecture obtained noteworthy newlineimprovements as a function of less area while executed on the Xilinx Spartan newlineFPGA series, namely, Spartan 3 devices, Virtex-5, and Virtex-4 devices. newlineFrom the obtained results, it is inferred that the proposed S-Box technique has newlinea smaller area than the existing conventional works. newline