Analysis and optimization of Floorplanning algorithms for VLSI physical design

Abstract

Rapid advances in semiconductor technologies have led to a newlinedramatic increase in the complexity of Very Large Scale Integration VLSI newlinecircuits With fabrication technology entering deep submicron era devices are newlinescaled down more functionalities are integrated into one chip and chips run newlineat higher clock frequencies Due to the increasing high complexity of modern newlinechip design VLSI Computer Aided Design CAD tools are important for newlinedelivering high system performance and there is a requirement for design newlineautomation tools Thus careful up front design planning and analyzing newlinephysical implementation effects before the actual layout is essential in newlinedesigning today s multi million gate Integrated Circuits ICs newlineMost of the problems in VLSI physical design process are newlineNon Deterministic Polynomial time NP hard problem The future newlinetremendous growth of VLSI circuits will rely on the development of physical newlinedesign automation tools In the physical design process Floorplanning is an newlineimportant step as it sets up the ground work for a good layout It is the newlineproblem of placing a set of circuit modules on a chip to minimize the total newlinearea and interconnect cost Various aspects of VLSI floorplanning problem newlinehave been studied in this thesis newline newline