Studies on high performance CMOS circuits in DSM Technology using Domino logic

Abstract

Dynamic logic circuits have been popularly used in advanced high speed processors as they occupy less area and have higher speed in comparison with the static CMOS counterparts. Domino logic is one of newlinethe popular dynamic logic. The major problems with domino gates are higher dynamic power, static power and lower noise immunity than newlinestatic logic circuits. In this work, an attempt has been made to design novel circuit techniques for robust, energy-efficient and high performance domino logic circuits in deep submicron technology. This work has been divided into three parts. In the first part, various novel energy-efficient, high performance domino logic circuit techniques have been developed and implemented. Performance design metrics in the presence of leakage currents have been analyzed. The EDP (Energy Delay Product) has been compared with the PDP (Power Delay Product) and a new metric called PEP (Power Energy Product) has been introduced. Comparing these three performance metrics, it has been observed that EDP places a higher weight on delay reduction, PEP places a higher weight newlineon power reduction, and PDP tries to strike a balance between the two. We further studied the relationship between the various metrics newlinein the VDD versus Vt plane. The effect of PVT (Process, Voltage, and Temperature) variation on the metrics as well as the optimal operating curve has been investigated. Then various dual-Vt energy-efficient newlineCMOS designs which have an edge over the standard single low ix threshold voltage designs have been proposed. Then, novel domino techniques with minimized swing that dissipate lower power than the standard domino designs have been proposed. Novel circuit techniques employing dual thresholds, dual power supplies, and dual grounds to reduce power dissipation, delay and to enhance noise immunity in domino circuits have been designed and developed.