Performance Parametric Optimization of Lateral and Vertical Power MOSFETs

dc.contributor.guide	Naugarhiya, Alok
dc.coverage.spatial
dc.creator.researcher	Parmar, Onika
dc.date.accessioned	2023-02-18T05:49:38Z
dc.date.available	2023-02-18T05:49:38Z
dc.date.awarded	2022
dc.date.completed	2021
dc.date.registered	2016
dc.description.abstract	attached newline
dc.description.note
dc.format.accompanyingmaterial	None
dc.format.dimensions	30 cm x 21 cm
dc.format.extent	XXI, 71
dc.identifier.uri	http://hdl.handle.net/10603/460867
dc.language	English
dc.publisher.institution	Electronics and Communication Engineering
dc.publisher.place	Raipur
dc.publisher.university	National Institute of Technology Raipur
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Electronics
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.subject.keyword	High- K VDMOS
dc.subject.keyword	power MOSFET
dc.subject.keyword	semiconducter device
dc.subject.keyword	SJ-VDMOS
dc.subject.keyword	VDMOS
dc.title	Performance Parametric Optimization of Lateral and Vertical Power MOSFETs
dc.title.alternative
dc.type.degree	Ph.D.