Design of low power delay product multiplier and divider units

dc.contributor.guide	Venkateswaran,P R and Prasad,Keerthana
dc.coverage.spatial	Information Science
dc.creator.researcher	Chaitanya C V S
dc.date.accessioned	2020-09-07T04:27:24Z
dc.date.available	2020-09-07T04:27:24Z
dc.date.awarded	24/06/2020
dc.date.completed	2020
dc.date.registered	23/11/2013
dc.description.abstract	Available
dc.description.note	Bibliography p.113-119
dc.format.accompanyingmaterial	None
dc.format.dimensions	-
dc.format.extent	119 p.
dc.identifier.uri	http://hdl.handle.net/10603/297921
dc.language	English
dc.publisher.institution	Manipal Institute of Technology
dc.publisher.place	Manipal
dc.publisher.university	Manipal Academy of Higher Education
dc.relation	No. of References 68
dc.rights	university
dc.source.university	University
dc.subject.keyword	Computer Science
dc.subject.keyword	Computer Science Information Systems
dc.subject.keyword	Engineering and Technology
dc.title	Design of low power delay product multiplier and divider units
dc.title.alternative
dc.type.degree	Ph.D.