Designing and Simulation of Low Power PVT Variations Aware FinFET Circuits

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dc.contributor.guideSharma, Vijay Kumar
dc.coverage.spatial
dc.creator.researcherKajal
dc.date.accessioned2024-04-15T12:51:04Z
dc.date.available2024-04-15T12:51:04Z
dc.date.awarded2024
dc.date.completed2024
dc.date.registered2018
dc.description.abstractnewline
dc.description.note
dc.format.accompanyingmaterialDVD
dc.format.dimensions
dc.format.extent
dc.identifier.urihttp://hdl.handle.net/10603/557818
dc.languageEnglish
dc.publisher.institutionSchool of Electronics and Communication Engineering
dc.publisher.placeKatra
dc.publisher.universityShri Mata Vaishno Devi University
dc.relation
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.titleDesigning and Simulation of Low Power PVT Variations Aware FinFET Circuits
dc.title.alternative
dc.type.degreePh.D.

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