High Performance Binary Logarithmic and BCD Multiplier Architectures

dc.contributor.guide	Srinivas, M. B
dc.coverage.spatial
dc.creator.researcher	Ahmed, Syed Ershad
dc.date.accessioned	2022-04-26T08:42:27Z
dc.date.available	2022-04-26T08:42:27Z
dc.date.awarded
dc.date.completed	2017
dc.date.registered	2009
dc.description.abstract	newline
dc.description.note
dc.format.accompanyingmaterial	DVD
dc.format.dimensions
dc.format.extent	144p
dc.identifier.uri	http://hdl.handle.net/10603/376189
dc.language	English
dc.publisher.institution	Electrical and Electronics Engineering
dc.publisher.place	Pilani
dc.publisher.university	Birla Institute of Technology and Science
dc.relation
dc.rights	university
dc.source.university	University
dc.subject.keyword	Engineering
dc.subject.keyword	Engineering and Technology
dc.subject.keyword	Engineering Electrical and Electronic
dc.title	High Performance Binary Logarithmic and BCD Multiplier Architectures
dc.title.alternative
dc.type.degree	Ph.D.