High performance error tolerant arithmetic circuits for approximate computing applications

Abstract

The carry select adder is a rapid addition mechanism employed in numerous data processing units to perform swift arithmetic operations. Approximate adders are used to compute the arithmetic function whose values slightly differ from the accurate value and they are tolerable in approximate result applications like image processing. To compensate for the rapid growth of technology, faster arithmetical circuits with less area, low power, and low cost circuits are needed. This paper introduces a novel design for the Modified Full Adder (MFA), aimed at imprecision computation. It disposes of carry generation amid the accumulation by permitting faults in the carry segment. The proposed circuit, 16-bit Carry Select Imprecision Adder (CSIA) is designed employing MFA units that are necessary to reduce the requirement for Ripple Carry Adders (RCA). CSIA method is employed to the Image Intermixture Implementation to represent the performance of the imprecision adder. Moreover, to achieve better clarification of an analytical model, error analysis is developed for CSIA. newline