Simulation and Modelling of Gate All around Junction less FET for RF and Linear Applications

Abstract

Modern technology necessitates smaller transistor dimensions, which increases the newlinecomplexity of short channel effects (SCEs), leakage current, and abrupt source/drain newlinejunction formation. Although increasing the power supply can reduce the static power newlinedissipation, it degrades the ON-state to OFF-state current ratio as a result of the Boltz- newlinemann tyranny of 60mV/decade sub-threshold swing in traditional MOSFETs, which is newlinecaused by the thermionic conduction process. In addition, scaling MOSFETs to the newlinesub-10 nm regime necessitates extremely steep doping profiles at the metallic connec- newlinetions. However, achieving such an incredibly steep doping profile is quite challenging. newlineTherefore, junctionless FETs (JLFETs) without any metallurgical junctions were pro- newlineposed. A junction less transistor has no junctions, unlike a conventional MOSFET, and newlineflow of current is directly controlled by the doping concentration rather than the gate ca- newlinepacitance. However, when the gate length is downsized to nanoscale dimensions, junc- newlinetionless transistors experience drawbacks similar to those of conventional MOSFETs. newlineFor instance, a high doping level in the channel is required to increase the drive current,but this also increases the leakage current. This results in a decreased ability to regulate the device s ON and OFF current which results in a lower ION/IOFF ratio. As the gate length is scaled down to the 10 nm regime, short channel junctionless transistors also show increased subthreshold slope (SS) and drain-induced barrier lowering (DIBL). In order to overcome all these stringents,junctionless transistors with Gate-all-around the device commonly known as GAA-JLFET are evolved as potential contenders to replace existing junction based FET devices for high frequency applications. In order to reduce the subthreshold slope value beyond 60mV/dec , a layer of ferroelectic material as a gate stack introduces negative capacitance in the device which helps in minimizing the SS value thereby improving the overall performance of the device.