FinFet Based High Performance Sram Bit Cell And Peripheral Circuitry

Abstract

With the widespread use of battery powered applications such as handheld smart phones and implantable medical devices, low-power operation is a major issue associated with the current System-on-Chip (SoC) designs. Since SRAM occupies a significant portion of an SoC, it critically affects the total power consumption of the SoC. In order to fulfill the requirements of high integration density and low power design, nanoscale devices are used to implement SRAM bit-cells. Continued SRAM bit-cell area scaling for increased storage density and reduction in operating voltage for lower power consumption becomes difficult to achieve at successive technology nodes. Further, progressive scaling to nanometer regime has made SRAM designs vulnerable especially to process variations and radiation effect. In this thesis, we explore research issues related to performance of SRAM systems currently fabricated in nanometer regime and attempt to design a robust SRAM system for SoC s low power and high performance applications in general and space applications in particular. newlineOur in depth literature survey of state of art of the technology revealed a few critically important concerns: (i) Process variations induced VT variability has severe impact on function failures of SRAM bit-cells at low VDD. (ii) VT variability also affects the sensing operation of sense amplifiers and degrades yield of SRAM systems. (iii) The scaling has made bit-cells more susceptible to radiation particles, which can cause single event multiple node upset (SEMNU) in addition to single event upset (SEU) and limit reliability of an SRAM system particularly in space applications. The exhaustive study of the literature indentifies tri-gated FinFET as an appropriate device in implementation of SRAM systems because of several features like lesser VT variability, lower leakage current and improved ION/IOFF ratio. newline