Radiation induced single event transient study on vco topologies using pll

Abstract

Ionizing radiation induced Single Event Upsets (SEU) and Single newlineEvent Transient (SET) in microelectronic circuits leads to signal amplitude newlinevariations or abrupt changes in frequency and phase. This susceptibility of newlinemicroelectronics used in defense and space applications especially in newlineradiation rich environment for SEU and SET is very high. The objective of newlinethis research work is to include circuit topologies that help mitigate the effects newlineof single event transients in VCOs used in PLL for clock generation using newlineconventional CMOS submicron process technologies. newlineProfound radiation robustness of a PLL circuit is determined by the newlineminimum phase displacement due to the radiation event. The study newlineinvestigates the impact of SET on differential ring VCO (DRVCO), a critical newlinesubcircuit of PLL for varying Linear Energy Transfer (LET) values. newlineThe missing pulses produced at the charge pump PLL (CPLL) output by newlineDRVCO due to ion hit is examined using Impulse Sensitivity Function (ISF). newlineTo reduce the erroneous cycled produced at the PLL output, this study newlineproposed two solutions: (i) by increasing the number of delay cell stages in newlinethe VCO stage (ii) a new SET hardened complementary delay cell for newlineDRVCO. newline