Investigations on VLSI implementation of map decoder architecture for low power applications

Abstract

Turbo codes have amazing error correcting capabilities and are suited for applications to various communication systems Turbo codes are radical in the sense that they allow reliable data transmission within a half decibel of the Shannon Limit The iterative nature of turbo decoding algorithms increases their complexity A generic structure for turbo encoder is based on parallel concatenation of two Recursive Systematic Convolutional newline encoders Two identical RSC encoders produce the redundant data as parity bits The input data stream and parity bits are combined in series to form the turbo coded word The code structure of turbo code is formed by two constituent convolutional encoders concatenated in parallel through a pseudorandom inter leaver Two iterative decoding algorithms viz Soft Output Viterbi Algorithm and Maximum A posteriori Probability newlineAlgorithm require complex decoding operations over several iteration cycles All MAP decoders are based on BCJR algorithm It tries to minimize the code word error by maximizing the probability and also known as a maximum likelihood algorithm MAP decoder involves extensive multiplication and logarithmic computation which are complicated in hardware implementation MAP decoder is employed in 4G wireless newlinestandards such as IEEE 802 16e WiMax and 3GPP Long Term Evolution Increased hardware complexity and the need to reduce the power consumption and power dissipation are the significant challenges of turbo decoder newline newline