Certain investigation on finfet based dwt lifting architecture using power gating and reversible logic

Abstract

In the consumer product design where Digital Signal Processing (DSP) and Digital Image Processing (DIP) are the most dominant areas, the Digital circuit design based on VLSI technology has to be flexible. Apart from implementing the algorithms of DSP and DIP in the VLSI device, power and area should be reduced. Since the requirements towards miniature devices are increasing the demand for the low power device is also increasing day by day. Various methods implemented in past were analyzed, and the results were compared. The research work is focused on designing a new architecture for Discrete Wavelet Transform (DWT), Multiply And Accumulation (MAC) unit using proposed adder and multiplier. When compared to convolution-based DWT architecture the proposed lifting-based DWT architecture has less computation and speed of operation. The multi-gate transistor reduces subthreshold and the gate tunneling leakage current. The device increases the driving current when compared to the standard single gate MOSFETs below submicron technologies. The promising multi-gate device which emerged to replace MOSFET device is the FinFET. Due to its thin silicon body and dual electrically coupled gate it suppresses the Short Channel Effects (SCE) which reduces the subthreshold leakage current. Full adder of energy recovery during static operation is designed in literature which uses only 10 Transistors. The FinFET equivalent circuit which consumes less power and low leakage uses a set of XOR XNOR gates and the frequency of operation is higher which is suitable for the DWT system. The FinFET- based adder with Feynman gate for sum and Fredkin gate for carry was implemented, which generates the carry output based on the output from the Feynman gate. newline