Synthesis test and architectural aspects of reversible logic

dc.contributor.guideBhattacharya, Bhargab B and Sarma, Samar Sen
dc.coverage.spatialTechnology
dc.creator.researcherGhosh, Satrajit
dc.date.accessioned2017-07-26T05:16:01Z
dc.date.available2017-07-26T05:16:01Z
dc.date.awardedn.d.
dc.date.completed2012
dc.date.registeredn.d.
dc.description.abstractAbstract available
dc.description.noteData not available
dc.description.provenanceMade available in DSpace on 2017-07-26T05:16:01Z (GMT). No. of bitstreams: 24 01_title page.pdf: 21568 bytes, checksum: a61e2d1bfdcf97fab1ef8ab205152746 (MD5) 02_dedication.pdf: 5827 bytes, checksum: 43109e71a976e86d640eae900378f27a (MD5) 03_abstract.pdf: 49316 bytes, checksum: e4a3633a06381228f10f1f26b0154e76 (MD5) 04_acknowledgement.pdf: 16931 bytes, checksum: 1718a3bb4c67a9a6c5841f7622ee8b80 (MD5) 05_preface.pdf: 187046 bytes, checksum: d9b73da22860cf01d413e1138c3ec370 (MD5) 06_content.pdf: 65696 bytes, checksum: 7f7f24b380d63c6c4adadaf0184ab620 (MD5) 07_glossary.pdf: 27560 bytes, checksum: 1a84b5c9563d73ec38a1d5ef384d8de8 (MD5) 08_list of figures.pdf: 135751 bytes, checksum: 7b3b00cbc36989bbc6607cbfd0efffc4 (MD5) 09_list of table.pdf: 53508 bytes, checksum: 10f69493944c5abf1a893e0ca638f3b9 (MD5) 10_chapter 1.pdf: 762783 bytes, checksum: 219d9e2efd50dc713d1d3ad59426fbd9 (MD5) 11_chapter 2.pdf: 1494467 bytes, checksum: 55ea3b7e88be980082cceb51ad1452c9 (MD5) 12_chapter 3.pdf: 4090958 bytes, checksum: 4833195874216be05a93500971f3cc84 (MD5) 13_chapter 4.pdf: 721591 bytes, checksum: 93601319bd32509c3b68ae8d75f4644a (MD5) 14_chapter 5.pdf: 1442593 bytes, checksum: 78f3451f72509efc33cb8b39b48dfc1a (MD5) 15_chapter 6.pdf: 2887936 bytes, checksum: d82e211310c89725a4ba635ef2755eb8 (MD5) 16_chapter 7.pdf: 536619 bytes, checksum: 5c3bf3d87018b46b3ddf848b51d503bb (MD5) 17_chapter 8.pdf: 424652 bytes, checksum: 6e0d047bec9da74579172d36251cde9b (MD5) 18_summary and future work.pdf: 116653 bytes, checksum: ba9c489b475a9059c817f29e7251f0da (MD5) 19_appendix a.pdf: 72697 bytes, checksum: e1e43d91e234ea6a9943d9a91ede6053 (MD5) 20_appendix b.pdf: 126443 bytes, checksum: f7bcc2a9183312ce4cd4486db659a719 (MD5) 21_appendix c.pdf: 71445 bytes, checksum: 7057efe6e65ae1099961cf0de17f5868 (MD5) 22_bibliography.pdf: 649981 bytes, checksum: a16dda33a7b9482ed2fc425348604dd0 (MD5) 23_list of corrections.pdf: 179301 bytes, checksum: c640eb9e58bb7bbfd6598b6a5c286a7e (MD5) license.txt: 1837 bytes, checksum: ebde26e9c598048970cb6f8173ba5cb2 (MD5)en
dc.format.accompanyingmaterialNone
dc.format.dimensions34cm.
dc.format.extentxiv, 124p.
dc.identifier.urihttp://hdl.handle.net/10603/162371
dc.languageEnglish US
dc.publisher.institutionDepartment of Technology
dc.publisher.placeKolkata
dc.publisher.universityUniversity of Calcutta
dc.relationReference given
dc.rightsuniversity
dc.source.universityUniversity
dc.subject.keywordArchitectural
dc.subject.keywordAspects
dc.subject.keywordLogic
dc.subject.keywordReversible
dc.subject.keywordSynthesis
dc.titleSynthesis test and architectural aspects of reversible logic
dc.type.degreePh.D.

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