Design of Energy Efficient Transceiver Blocks for Wireless Sensor Nodes

Abstract

Sensor networks have been recognised as one of the most advanced newlinetechnologies of the 21st century with vast practical applications. The life of a newlinesensor network is mainly determined by its energy consumption. Commercially newlineavailable sensor nodes are battery driven devices. As most sensor nodes are newlinedeployed widely scattered and in isolated areas, replacing battery is not an newlineoption. This dissertation focuses on extending the lifespan of sensor networks newlineby reducing energy consumption in design and operation of sensor nodes. newlineThe study goes in depth to analyse the state of art technology to achieve newlineenergy efficiency in sensor nodes and identify scope for further research in this newlinefield. In the architecture of sensor nodes, multipliers are the main blocks for newlinedesigning an energy efficient processor. Vedic Mathematics provides principles newlineof high speed multiplication. The main reason for power dissipation in multiplier newlinecircuit is due to power dissipation of full adder circuit. Low power multipliers newlinehave been designed by using low power adders. Motivated by this, a high speed newlineVedic multiplier has been designed using multiplexer based adder. When newlinecompared with existing Vedic multipliers, proposed designs showed significant newlineimprovement in reduction of delay and energy consumption. newlineSensor nodes consume maximum power during data communication. So newlineprocessing data locally at each node in a sensor network is important for newlineminimizing power consumption. High processing speed and low area designs newlineare in ever growing demand. In order to predict outcomes, based on previous newlineinputs, ALU can be designed with neurons. Processing speed of ALU can be newlineimproved by replacing conventional multipliers with Vedic multipliers. This newlineresearch work suggests implementation of high speed ALU using Vedic newlineneurons. The analysis of the results shows that the proposed design leads to newlinex newlinereduction in the delay and reduction in LUT count (an indicator of area) of the newlineALU. newline