Improving performance of bufferless network on chips by architectural modifications

Abstract

Consumer electronics gadgets used for multi-media processing, gaming, and newlineAI-based applications, which have huge data processing demands rely on parallel newlineprocessing. Instead of using a single high-performance core, employing tens or newlinehundreds of efficient smaller cores working at lower frequencies leads to higher newlineperformance and energy efficiency. Multi-core processors are required to power newlinelatest consumer electronics devices to cater the exponential increase in their newlinedata processing demands. This has led to the emergence of Tiled Chip Multi newlineProcessors (TCMP), which contain tens or hundreds of cores integrated on a newlinechip. With the rise in the number of on-chip processing elements, there is newlinean ever-increasing demand for a scalable and modular on-chip communication newlinesystem. Network-on-Chip (NoC), a packet switched network, has evolved as a newlineviable alternative to overcome communication issues occurring between different newlineprocessing cores in TCMP designs that employ traditional on-chip interconnect newlinestructures. Every processing element of regular tile-based NoC is connected to newlinea high-speed router and routers are attached to communication links to route newlinepackets between various processing cores. The efficiency and performance of any newlineNoC system depend on the design of efficient routers, underlying topology and newlinerouting mechanism. newline